1. Field of the Invention
The present invention relates to fabricating semiconductor devices, and, more particularly, to increasing the step coverage of the interconnect metal by forming a plug in the contact hole. Use of chemical vapor deposition (CVD) in combination with sputtering eliminates the disadvantages associated with either technique alone.
2. Description of the Related Art
During fabrication of semiconductor devices employing multilevel metal interconnections, aluminum (Al) alloys are typically sputtered on wafers and then patterned as interconnects. These interconnect lines make contact with the substrate or another metal layer through a hole in dielectric layers called a "contact hole" or "via".
Normally, the step coverage of metal, which is generally defined as the percentage ratio of the minimum metal thickness at any point in the contact to the metal thickness on top of the dielectric layer, is about 50% or lower for sputtered Al alloys. Certain modifications in the contact shape, such as sloped walls or that obtained by combined wet and dry etching, help improve the step coverage, but such modifications produce larger diameter contacts, resulting in increased contact pitch and requiring broader metal lines to cover the contact area.
In order to obtain tighter geometries, it is desirable to have contacts with unsloped vertical sidewalls. The step coverage of sputtered aluminum on vertical walled cylindrical contacts is unfortunately very poor, and thus the interconnect as a whole is highly unreliable.
To overcome this problem, a plug of a conducting material may be used to fill the contact. One of the ways this could be done is to grow tungsten selectively in the contact area by CVD. There are several problems associated with this method, namely, encroachment at the oxide/silicon interface and worm hole damage to the underlying silicon as described by E.K. Broadbent and W.T. Stacy, "Selective Tungsten Processing by Low Pressure CVD", Solid State Technology, pp. 51-59 (December 1985).
Another process is to deposit blanket tungsten by a CVD process and etch it back in order to leave plugs in the contact holes only. Since tungsten has poor adhesion to silicon dioxide, an adhesion layer of tungsten silicide is employed between the oxide and the tungsten layer. The contact resistance of tungsten silicide to the doped substrate is poor, therefore, a flash tungsten layer is deposited only in the contact area prior to the tungsten silicide layer deposition to improve the contact resistance. The deposition process for flash tungsten is very similar to that of selective tungsten. This flash tungsten has the same problems associated with it as the selective tungsten process, namely, encroachment and worm hole damage.
Another way that a plug can be implemented is to deposit a blanket layer of polysilicon across the wafer (including in the contact holes) and then etch it back flush to the oxide surface, leaving polysilicon plugs in the contact holes. These plugs could then be appropriately doped to make contact to the underlying semiconductor. One of the disadvantages associated with this technique for use in CMOS and bipolar circuits is that in order to contact both N.sup.+ and P.sup.+ regions, at least one masking step is required to isolate the contacts of one doping polarity from those of the other polarity in order to prevent counterdoping. This masking step represents a significant increase in process complexity. Another disadvantage is that since the dopant is introduced from the top of the plug and must diffuse downward all the way through the plug, it is difficult to achieve a highly uniform dopant distribution in very tall (&gt;15,000 .ANG.) plugs, thereby greatly increasing the resistance of these contacts.
Recent schemes for the implementation of plug processes can be typified by that of Widmann and Sigusch, U.S. Pat. No. 4,562,640, "Method of Manufacturing Low Resistance Contacts in Integrated Semiconductor Circuits". In that reference, the patentees show a plug comprising a blanket-deposited conformal N.sup.+ polysilicon in contact with a previously selectively formed silicide. While it is contended that this structure is functional so long as all subsequent processing is carried out below 400.degree. C. (or only using rapid laser annealing above 400.degree. C.), the process has two drawbacks.
The first drawback is that the silicide contacting layer requires several separate steps for its formation. The second drawback is that with this approach, all subsequent processing is limited to below about 400.degree. C.. This limits one to the use of low temperature (about 300.degree. to 350.degree. C.) polysilicon deposition, which has inferior conformality as compared to polysilicon deposited by higher temperature (about 600.degree. to 650.degree. C.) processes. The low temperature restriction also limits the degree of dopant activation in the polysilicon layer, resulting in higher contact resistance.
While the patentees attempt to provide a solution to this problem by adding a barrier between the silicide and the poly, the chromium/chromium oxide barrier solution shown is selective in that it is only left in the contact hole. Thus, three steps are required to make the silicide contact, two steps to make the barrier, and two steps to make the polysilicon cap. In addition to this process complexity, the polysilicon dopants will diffuse through the chromium/chromium oxide barrier even at 450.degree. C..
Thus, there remains a need for a contact plug which avoids most, if not all, the foregoing problems.